diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 3f26be75..5848d89e 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -26,8 +26,71 @@ jobs: run: | python -m pip install --upgrade pip pip install -r requirements.txt - # ------------- Tests ---------------- - name: test and16 run: | pytest hw/test_components.py -k and16 + + - name: test or8way + run: | + pytest hw/test_components.py -k or8way + + - name: test mux2way + run: | + pytest hw/test_components.py -k test_mux2way + + - name: test mux4way + run: | + pytest hw/test_components.py -k test_mux4way + + - name: test mux8way + run: | + pytest hw/test_components.py -k test_mux8way + + - name: test deMux8way + run: | + pytest hw/test_components.py -k test_deMux8way + + - name: test orNway + run: | + pytest hw/test_components.py -k orNway + + - name: test barrelShifter + run: | + pytest hw/test_components.py -k barrelShifter + + - name: test deMux2way + run: | + pytest hw/test_components.py -k test_deMux2way + + - name: test deMux4way + run: | + pytest hw/test_components.py -k test_deMux4way + + - name: test bin2bcd + run: | + pytest hw/test_components.py -k bin2bcd + + - name: Combinacional + run: | + pytest hw/test_components.py + + - name: test add + run: | + pytest hw/test_ula.py -k test_add + + - name: test zerador + run: | + pytest hw/test_ula.py -k test_zerador + + - name: test inversor + run: | + pytest hw/test_ula.py -k test_inversor + + - name: test addcla4 + run: | + pytest hw/test_ula.py -k test_addcla4 + + + + diff --git a/.gitignore b/.gitignore index 168e776a..33b0efa1 100644 --- a/.gitignore +++ b/.gitignore @@ -7,3 +7,5 @@ htmlcov *.v .direnv/ *.ini +/env +/env] \ No newline at end of file diff --git a/GRUPO.yml b/GRUPO.yml index f0433867..2a48da76 100644 --- a/GRUPO.yml +++ b/GRUPO.yml @@ -1 +1,2 @@ -Nome-Grupo: "Macarrao" +Nome-Grupo: "Grupo Grã" +Scrum-Master: "Felipe Maluli de Carvalho Dias" \ No newline at end of file diff --git a/INTEGRANTES.json b/INTEGRANTES.json new file mode 100644 index 00000000..e903342b --- /dev/null +++ b/INTEGRANTES.json @@ -0,0 +1,42 @@ +[ + { + "user": "1", + "name": "Alexandre Magno Maciel dos Santos", + "git-username": "alemagno10", + "blackboard-username": "alexandremms" + }, + + { + "user": "2", + "name": "Lucca Hiratsuca Costa", + "git-username": "LuccaHiratsuca", + "blackboard-username": "luccahc" + }, + + { + "user": "3", + "name": "Júlia Ferreira de Paiva", + "git-username": "juliapaiva1", + "blackboard-username": "juliafp2" + }, + + { + "user": "4", + "name": "Felipe Maluli de Carvalho Dias", + "git-username": "FeMCDias", + "blackboard-username": "felipemcd1" +}, + +{ + "user": "5", + "name": "Felipe Figueiró", + "git-username": "", + "blackboard-username": "" +}, +{ + "user": "6", + "name": "Gustavo Lagoa", + "git-username": "", + "blackboard-username": "" +} +] \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 00000000..ead0077e --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +link do video - conceito A +https://youtube.com/shorts/-07dCv11VKs?feature=share \ No newline at end of file diff --git a/exit b/exit new file mode 100644 index 00000000..47bb29f0 --- /dev/null +++ b/exit @@ -0,0 +1,10 @@ + and16 + bin2bcd + deMux2way + deMux8way +* inc + main + or8way + orNway + test_inc + toplevel diff --git a/hw/components.py b/hw/components.py index aa9336e9..69484270 100644 --- a/hw/components.py +++ b/hw/components.py @@ -2,22 +2,19 @@ from myhdl import * - @block def and16(a, b, q): """ a: 16 bits b: 16 bits q: 16 bits - and bit a bit entre a e b """ foo = Signal(0) @always_comb def comb(): - q.next = foo - + q.next = a and b return comb @@ -25,14 +22,13 @@ def comb(): def or8way(a, b, c, d, e, f, g, h, q): """ a, b, c, ... h: 1 bit - or bit a bit entre a e b """ foo = Signal(intbv(0)) @always_comb def comb(): - q.next = foo + q.next = a or b or c or d or e or f or g or h return comb @@ -42,14 +38,14 @@ def orNway(a, q): """ a: 16 bits q: 1 bit - or bit a bit dos valores de a: a[0] or a[1] ... """ foo = Signal(intbv(0)) @always_comb def comb(): - q.next = foo + q.next = a[0] or a[1] or a[2] or a[3] or a[4] or a[5] or a[6] or a[7] or a[8] or a[9] or a[10] or a[11] or a[12] or a[13] or a[14] or a[15] + return comb @@ -61,10 +57,8 @@ def barrelShifter(a, dir, size, q): dir: 1 bit size: n bits q: 16 bits - se dir for 0, shifta para direita `size` se dir for 1, shifta para esquerda `size` - exemplo: a = 0000 1111 0101 1010, dir = 0, size = 3 q = 0111 1010 1101 0000 """ @@ -72,7 +66,7 @@ def barrelShifter(a, dir, size, q): @always_comb def comb(): - q.next = foo + q.next = a <> size return comb @@ -83,15 +77,14 @@ def mux2way(q, a, b, sel): q: 16 bits a: 16 bits b: 16 bits - sel: 2 bits - + sel: 1 bits Mux entre a e b, sel é o seletor """ foo = Signal(intbv(0)) @always_comb def comb(): - q.next = foo + q.next = a if sel == 0 else b return comb @@ -105,14 +98,20 @@ def mux4way(q, a, b, c, d, sel): c: 16 bits d: 16 bits sel: 4 bits - Mux entre a, b, c, d sel é o seletor """ foo = Signal(intbv(0)) @always_comb def comb(): - q.next = foo + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + else: + q.next = d return comb @@ -127,7 +126,22 @@ def mux8way(q, a, b, c, d, e, f, g, h, sel): @always_comb def comb(): - q.next = foo + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + elif sel == 3: + q.next = d + elif sel == 4: + q.next = e + elif sel == 5: + q.next = f + elif sel == 6: + q.next = g + else: + q.next = h return comb @@ -136,11 +150,8 @@ def comb(): def deMux2way(a, q0, q1, sel): """ deMux de 2 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 - Exemplo: - a = 0xFFAA, sel = 0 q0 = 0xFFAA q1 = 0 @@ -150,7 +161,13 @@ def deMux2way(a, q0, q1, sel): @always_comb def comb(): - q0.next = foo + if sel == 0: + q0.next = a + q1.next = 0 + + else: + q0.next = 0 + q1.next = a return comb @@ -159,7 +176,6 @@ def comb(): def deMux4way(a, q0, q1, q2, q3, sel): """ deMux de 4 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 """ @@ -167,7 +183,29 @@ def deMux4way(a, q0, q1, q2, q3, sel): @always_comb def comb(): - q0.next = foo + if sel == 11: + q0.next = 0 + q1.next = 0 + q2.next = 0 + q3.next = a + + if sel == 10: + q0.next = 0 + q1.next = 0 + q2.next = a + q3.next = 0 + + if sel == 00: + q0.next = a + q1.next = 0 + q2.next = 0 + q3.next = 0 + + else: + q0.next = 0 + q1.next = a + q2.next = 0 + q3.next = 0 return comb @@ -176,7 +214,6 @@ def comb(): def deMux8way(a, q0, q1, q2, q3, q4, q5, q6, q7, sel): """ deMux de 8 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 """ @@ -184,7 +221,14 @@ def deMux8way(a, q0, q1, q2, q3, q4, q5, q6, q7, sel): @always_comb def comb(): - q0.next = foo + q0.next = a if sel == 0 else 0 + q1.next = a if sel == 1 else 0 + q2.next = a if sel == 2 else 0 + q3.next = a if sel == 3 else 0 + q4.next = a if sel == 4 else 0 + q5.next = a if sel == 5 else 0 + q6.next = a if sel == 6 else 0 + q7.next = a if sel == 7 else 0 return comb @@ -198,10 +242,41 @@ def bin2hex(hex0, sw): """ importar do lab! """ - + @always_comb def comb(): - hex0.next[4:] = sw[4:] + if sw[4:0] == 0: + hex0.next = "1000000" + elif sw[4:0] == 1: + hex0.next = "1001111" + elif sw[4:0] == 2: + hex0.next = "0100100" + elif sw[4:0] == 3: + hex0.next = "0110000" + elif sw[4:0] == 4: + hex0.next = "0011001" + elif sw[4:0] == 5: + hex0.next = "0010010" + elif sw[4:0] == 6: + hex0.next = "0000010" + elif sw[4:0] == 7: + hex0.next = "1111000" + elif sw[4:0] == 8: + hex0.next = "1111111" + elif sw[4:0] == 9: + hex0.next = "0010000" + elif sw[4:0] == 10: + hex0.next = "0001000" + elif sw[4:0] == 11: + hex0.next = "0000011" + elif sw[4:0] == 12: + hex0.next = "1000110" + elif sw[4:0] == 13: + hex0.next = "0100001" + elif sw[4:0] == 14: + hex0.next = "0000110" + else: + hex0.next = "0001110" return comb @@ -211,7 +286,6 @@ def bin2bcd(b, bcd1, bcd0): """ componente que converte um vetor de b[8:] (bin) para dois digitos em BCD - Exemplo: bin = `01010010` BCD1 = 8 @@ -220,14 +294,17 @@ def bin2bcd(b, bcd1, bcd0): foo = Signal(intbv(0)[4:]) + tens = tuple(num//10 for num in range(100)) + ones = tuple(num%10 for num in range(100)) + @always_comb def comb(): - bcd1.next = foo - bcd0.next = foo + bcd1.next = tens[b] + bcd0.next = ones[b] return comb # -----------------------------# # Conceito A -# -----------------------------# +# -----------------------------# \ No newline at end of file diff --git a/hw/test_components.py b/hw/test_components.py index dda59118..3cacb5e1 100644 --- a/hw/test_components.py +++ b/hw/test_components.py @@ -203,16 +203,32 @@ def stimulus(): sim.run() +# def test_bin2bcd(): +# bc0 = Signal(intbv(0)[4:]) +# bc1 = Signal(intbv(0)[4:]) +# b = Signal(intbv(0)[9:]) + +# ic1 = bin2bcd(b, bc1, bc0) + +# @instance +# def stimulus(): +# yield delay(1) + +# sim = Simulation(ic1, stimulus) +# sim.run() + def test_bin2bcd(): bc0 = Signal(intbv(0)[4:]) bc1 = Signal(intbv(0)[4:]) b = Signal(intbv(0)[9:]) - - ic1 = bin2bcd(b, bc1, bc0) - + resultado = bin2bcd(b, bc1, bc0) @instance def stimulus(): - yield delay(1) + for dec in range(100): + b.next = dec + yield delay(1) + assert bc0 == dec % 10 + assert bc1 == dec // 10 - sim = Simulation(ic1, stimulus) - sim.run() + sim = Simulation(resultado, stimulus) + sim.run() \ No newline at end of file diff --git a/hw/test_ula.py b/hw/test_ula.py new file mode 100755 index 00000000..4e00124d --- /dev/null +++ b/hw/test_ula.py @@ -0,0 +1,200 @@ +#!/usr/bin/env python3 +import random +from myhdl import block, instance, Signal, intbv, delay, bin +from .ula import * + +random.seed(5) +randrange = random.randrange + + +def test_ula(): + x = Signal(intbv(1)[16:]) + y = Signal(intbv(2)[16:]) + saida = Signal(intbv(0)[16:]) + control = Signal(intbv(0)) + zr = Signal(bool(0)) + ng = Signal(bool(0)) + ula_1 = ula(x, y, control, zr, ng, saida) + + @instance + def stimulus(): + control.next = 0b000010 + yield delay(10) + assert saida == x + y + + control.next = 0b000000 + yield delay(10) + assert saida == (x & y) + + control.next = 0b100010 + yield delay(10) + assert saida == y + + control.next = 0b001010 + yield delay(10) + assert saida == x + + control.next = 0b100110 + yield delay(10) + assert saida == ~y + + control.next = 0b011010 + yield delay(10) + assert saida == ~x + + control.next = 0b101010 + yield delay(10) + assert saida == 0 + + control.next = 0b101000 + yield delay(10) + assert saida == 0 + + control.next = 0b101001 + yield delay(10) + assert saida == intbv(-1)[16:] + + # ------ zr ng --------# + assert zr == 0 and ng == 1 + + control.next = 0b101000 + yield delay(10) + assert zr == 1 and ng == 0 + + control.next = 0b000010 + yield delay(10) + assert zr == 0 and ng == 0 + + sim = Simulation(ula_1, stimulus) + sim.run() + + +def test_zerador(): + z = Signal(bool(0)) + a = Signal(intbv(0)) + y = Signal(intbv(0)) + zerador_1 = zerador(z, a, y) + + @instance + def stimulus(): + a.next = randrange(2**16 - 1) + z.next = 0 + yield delay(10) + assert y == a + z.next = 1 + yield delay(10) + assert y == 0 + + sim = Simulation(zerador_1, stimulus) + sim.run() + + +def test_comparador(): + a = Signal(intbv(0)) + ng = Signal(bool(0)) + zr = Signal(bool(0)) + comparador_1 = comparador(a, zr, ng, 16) + + @instance + def stimulus(): + a.next = 0 + yield delay(10) + assert ng == 0 or zr == 1 + a.next = 0xFFFF + yield delay(10) + assert ng == 1 or zr == 0 + a.next = 32 + yield delay(10) + assert ng == 0 or zr == 0 + + sim = Simulation(comparador_1, stimulus) + sim.run() + + +def test_inversor(): + z = Signal(bool(0)) + a = Signal(intbv(0)) + y = Signal(intbv(0)) + + inversor_1 = inversor(z, a, y) + + @instance + def stimulus(): + for i in range(256): + a.next = randrange(2**16 - 1) + z.next = randrange(2) + yield delay(1) + if z == 0: + assert a == y + else: + assert a == ~y + + sim = Simulation(inversor_1, stimulus) + sim.run() + + +def test_inc(): + a = Signal(intbv(0)) + q = Signal(intbv(0)) + + inc16_1 = inc(a, q) + + @instance + def stimulus(): + for i in range(256): + a.next = randrange(2**16 - 2) + yield delay(1) + assert q == a + 1 + + sim = Simulation(inc16_1, stimulus) + sim.run() + + +def test_add(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + add16_1 = add(a, b, q) + + @instance + def stimulus(): + for i in range(256): + a.next, b.next = [randrange(2**15 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + + sim = Simulation(add16_1, stimulus) + sim.run() + +def test_addcla4(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + addcla4_1 = addcla4(a, b, q) + + @instance + def stimulus(): + for i in range(16): + a.next, b.next = [randrange(2**3 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + sim = Simulation(addcla4_1, stimulus) + sim.run() + +def test_addcla16(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + addcla16_1 = addcla4(a, b, q) + + @instance + def stimulus(): + for i in range(256): + a.next, b.next = [randrange(2**15 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + sim = Simulation(addcla16_1, stimulus) + sim.run() \ No newline at end of file diff --git a/hw/toplevel.py b/hw/toplevel.py index 6d1d0b1c..287ac994 100755 --- a/hw/toplevel.py +++ b/hw/toplevel.py @@ -1,24 +1,34 @@ #!/usr/bin/env python3 -# -*- coding: utf-8 -*- +# -- coding: utf-8 -- from myhdl import * from components import * +from ula import * @block def toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N): sw_s = [SW(i) for i in range(10)] key_s = [KEY(i) for i in range(10)] - ledr_s = [Signal(bool(0)) for i in range(10)] + ledrs = [Signal(bool(0)) for i in range(10)] - bc0 = Signal(intbv(0)[4:]) - bc1 = Signal(intbv(0)[4:]) - hex0 = Signal(intbv(0)[7:]) - hex1 = Signal(intbv(0)[7:]) + #Variaveis que não são usadas: + # bc0 = Signal(intbv(0)[4:]) + # bc1 = Signal(intbv(0)[4:]) + # hex0 = Signal(intbv(0)[7:]) + # hex1 = Signal(intbv(0)[7:]) - ic1 = bin2bcd(SW[8:0], bc1, bc0) - ihex1 = bin2hex(hex1, bc1) - ihex0 = bin2hex(hex0, bc0) + # Funções que usavam variáveis erradas: + # ic1 = bin2bcd(SW[8:0], bc1, bc0) + # ihex1 = bin2hex(hex1, bc1) + # ihex0 = bin2hex(hex0, bc0) + + # ic1 = bin2bcd(SW, bc1, bc0) + # ihex1 = bin2hex(HEX1, bc1) + # ihex0 = bin2hex(HEX0, bc0) + + + ula_ = ula(Signal(intbv(1)[8:]), Signal(intbv(2)[8:]), SW, ledr_s[8], ledr_s[9], ledr_s[0:8], Signal(modbv(0)[8:])) # ---------------------------------------- # @always_comb @@ -39,7 +49,10 @@ def comb(): HEX4 = Signal(intbv(1)[7:]) HEX5 = Signal(intbv(1)[7:]) CLOCK_50 = Signal(bool()) + + + RESET_N = ResetSignal(0, active=0, isasync=True) top = toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N) -top.convert(hdl="VHDL") +top.convert(hdl="VHDL") \ No newline at end of file diff --git a/hw/ula.py b/hw/ula.py new file mode 100644 index 00000000..5f2e8eee --- /dev/null +++ b/hw/ula.py @@ -0,0 +1,165 @@ +#!/usr/bin/env python3 + +from myhdl import * +from .components import * +@block +def ula(x, y, c, zr, ng, saida, width=16): + zx_out = Signal(modbv(0)[width:]) + nx_out = Signal(modbv(0)[width:]) + zy_out = Signal(modbv(0)[width:]) + ny_out = Signal(modbv(0)[width:]) + and_out = Signal(modbv(0)[width:]) + add_out = Signal(modbv(0)[width:]) + mux_out = Signal(modbv(0)[width:]) + no_out = Signal(modbv(0)[width:]) + + c_zx = c(5) + c_nx = c(4) + c_zy = c(3) + c_ny = c(2) + c_f = c(1) + c_no = c(0) + + z0 = zerador(c_zx, zx_out, x) + i1 = inversor(c_nx, zx_out, nx_out) + + z2 = zerador(c_zy, zy_out, y) + i2 = inversor(c_ny, zy_out, ny_out) + + m1 = mux2way(mux_out, and_out, add_out, c_f) + i3 = inversor(c_no, mux_out, no_out) + + c1 = comparador(no_out, zr, ng, width) + + @always_comb + def comb(): + and_out.next = nx_out & ny_out + add_out.next = nx_out + ny_out + saida.next = no_out + return instances() + + +# -z faz complemento de dois +# ~z inverte bit a bit +@block +def inversor(z, a, y): + @always_comb + def comb(): + if z == 1: + y.next = ~a + else: + y.next = a + + return instances() + + +@block +def comparador(a, zr, ng, width): + # width insica o tamanho do vetor a + @always_comb + def comb(): + if a == 0: + zr.next = 1 + else: + zr.next = 0 + if a[width-1]: + ng.next = 1 + else: + ng.next = 0 + + return instances() + + +@block +def zerador(z, a, y): + @always_comb + def comb(): + if z == 0: + a.next = y + else: a.next = 0 + return instances() + + +@block +def add(a, b, q): + @always_comb + def comb(): + q.next = a + b + return instances() + + +@block +def inc(a, q): + @always_comb + def comb(): + q.next = a + 1 + + return instances() + + +# ---------------------------------------------- +# Conceito B +# ---------------------------------------------- + + +@block +def halfAdder(a, b, soma, carry): + s = Signal(bool()) + c = Signal(bool()) + + @always_comb + def comb(): + s = a ^ b + c = a & b + + soma.next = s + carry.next = c + + return instances() + + +@block +def fullAdder(a, b, c, soma, carry): + s = [Signal(bool(0)) for i in range(3)] + haList = [None for i in range(2)] + + haList[0] = halfAdder(a, b, s[0], s[1]) # 2 + haList[1] = halfAdder(c, s[0], soma, s[2]) # 3 + + @always_comb + def comb(): + carry.next = s[1] | s[2] # 4 + + return instances() + + +@block +def addcla4(a, b, q): + @always_comb + def comb(): + q.next = a+b + return instances() + + +@block +def addcla16(a, b, q): + @always_comb + def comb(): + q.next = a + b + + return instances() + + +# ---------------------------------------------- +# Conceito A +# ---------------------------------------------- + + +@block +def ula_new(x, y, c, zr, ng, sr, sf, bcd, saida, width=16): + pass + + +@block +def bcdAdder(x, y, z): + pass