From 7a54aadc7c685bda9281c087dec605dd01bccec2 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 17 Jan 2026 17:24:41 +0000 Subject: [PATCH 1/3] Update scalafmt-core to 3.10.4 --- .scalafmt.conf | 2 +- docs/getting-started/hello-world/scala-project/.scalafmt.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 31035ca52..470aeb002 100755 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.10.1 +version = 3.10.4 runner.dialect = scala3 maxColumn = 100 diff --git a/docs/getting-started/hello-world/scala-project/.scalafmt.conf b/docs/getting-started/hello-world/scala-project/.scalafmt.conf index f088f4624..826d7e1c2 100644 --- a/docs/getting-started/hello-world/scala-project/.scalafmt.conf +++ b/docs/getting-started/hello-world/scala-project/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.10.1 +version = 3.10.4 runner.dialect = scala3 maxColumn = 100 From 791ad4a57a45e7561ca2ebb6cdcb6f217dd15a8a Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 17 Jan 2026 17:25:07 +0000 Subject: [PATCH 2/3] Reformat with scalafmt 3.10.4 Executed command: scalafmt --non-interactive --- .../compiler/analysis/DFValAnalysis.scala | 11 ++++---- .../compiler/analysis/DomainAnalysis.scala | 21 ++++++++------- .../src/main/scala/dfhdl/compiler/ir/DB.scala | 24 +++++++++++------ .../scala/dfhdl/compiler/ir/DFMember.scala | 27 ++++++++++++------- .../main/scala/dfhdl/compiler/ir/DFType.scala | 5 ++-- .../compiler/printing/DFDataPrinter.scala | 20 +++++++------- .../dfhdl/compiler/stages/AddClkRst.scala | 3 +-- .../compiler/stages/DropStructsVecs.scala | 15 ++++++----- .../scala/dfhdl/compiler/stages/ToED.scala | 15 ++++++----- .../stages/verilog/VerilogValPrinter.scala | 3 ++- .../stages/vhdl/VHDLDataPrinter.scala | 13 ++++----- .../compiler/stages/vhdl/VHDLValPrinter.scala | 9 ++++--- .../ExplicitCondExprAssignSpec.scala | 9 ++++--- .../StagesSpec/ExplicitNamedVarsSpec.scala | 9 ++++--- .../scala/dfhdl/compiler/patching/Patch.scala | 20 ++++++++------ .../src/main/scala/dfhdl/core/DFDecimal.scala | 3 ++- core/src/main/scala/dfhdl/core/DFDouble.scala | 3 ++- core/src/main/scala/dfhdl/core/DFEnum.scala | 6 ++--- .../src/main/scala/dfhdl/core/MutableDB.scala | 5 ++-- .../src/test/scala/CoreSpec/DFMatchSpec.scala | 6 ++--- .../main/scala/dfhdl/internals/helpers.scala | 9 ++++--- .../dfhdl/platforms/resources/ToggleIO.scala | 3 ++- .../scala/dfhdl/tools/toolsCore/Vivado.scala | 3 ++- lib/src/test/scala/AES/defs.scala | 3 +-- .../scala/plugin/CustomControlPhase.scala | 5 ++-- .../src/main/scala/plugin/LoopFSMPhase.scala | 3 ++- .../scala/plugin/MetaContextGenPhase.scala | 12 ++++++--- .../scala/plugin/MetaContextPlacerPhase.scala | 3 ++- 28 files changed, 156 insertions(+), 112 deletions(-) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala index 81cdd3439..fc192cdd0 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala @@ -414,11 +414,12 @@ extension (origVal: DFVal) forceIncludeOrigVal: Boolean )(using MemberGetSet): List[DFVal] = if (origVal.isAnonymous && !origVal.isGlobal || forceIncludeOrigVal) - origVal :: origVal.getRefs.map(_.get).view - .flatMap { - case dfVal: DFVal => dfVal.collectRelMembersRecur(false) - case _ => Nil - }.toList + origVal :: + origVal.getRefs.map(_.get).view + .flatMap { + case dfVal: DFVal => dfVal.collectRelMembersRecur(false) + case _ => Nil + }.toList else Nil @targetName("collectRelMembersDFVal") def collectRelMembers(includeOrigVal: Boolean)(using MemberGetSet): List[DFVal] = diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala index 15c7e3fa4..769564325 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala @@ -21,21 +21,24 @@ final class DomainAnalysis(designDB: DB): if clkCfg != None || rstCfg != None => collectedDesignDomains.get(key) match case Some(clkRstOpt) => - (clkCfg != None && clkRstOpt.clkOpt.isEmpty) || (rstCfg != None && clkRstOpt.rstOpt.isEmpty) + (clkCfg != None && clkRstOpt.clkOpt.isEmpty) || + (rstCfg != None && clkRstOpt.rstOpt.isEmpty) case None => true case _ => setEmpty(key) // TODO: probably ugly to do this here false private def addClk(key: DFDomainOwner, clk: DFVal.Dcl): Unit = - collectedDesignDomains += key -> collectedDesignDomains - .get(key) - .map(_.addClk(clk)) - .getOrElse(ClkRstOpt(Some(clk), None)) + collectedDesignDomains += key -> + collectedDesignDomains + .get(key) + .map(_.addClk(clk)) + .getOrElse(ClkRstOpt(Some(clk), None)) private def addRst(key: DFDomainOwner, rst: DFVal.Dcl): Unit = - collectedDesignDomains += key -> collectedDesignDomains - .get(key) - .map(_.addRst(rst)) - .getOrElse(ClkRstOpt(None, Some(rst))) + collectedDesignDomains += key -> + collectedDesignDomains + .get(key) + .map(_.addRst(rst)) + .getOrElse(ClkRstOpt(None, Some(rst))) private def setEmpty(key: DFDomainOwner): Unit = collectedDesignDomains += key -> ClkRstOpt(None, None) end extension diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala index ce6263b1d..272a1cafe 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala @@ -124,7 +124,8 @@ final case class DB( if (owner == namedDFTypeMember.getOwnerDesign) namedDFTypeMap // same design block -> nothing to do else - namedDFTypeMap + (dfType -> None) // used in more than one block -> global named type + namedDFTypeMap + + (dfType -> None) // used in more than one block -> global named type case Some(None) => namedDFTypeMap // known to be a global type // found new named type case None => @@ -782,7 +783,8 @@ final case class DB( case internal: DFDesignBlock => internal.usesClkRst.usesClk case _ => false } || reversedDependents.getOrElse(domainOwner, Set()).exists(_.usesClkRst.usesClk) || - domainOwner.isTop && (domainOwner.getExplicitCfg.clkCfg match + domainOwner.isTop && + (domainOwner.getExplicitCfg.clkCfg match case ClkCfg.Explicit(inclusionPolicy = ClkRstInclusionPolicy.AlwaysAtTop) => true case _ => false) @@ -794,7 +796,8 @@ final case class DB( case internal: DFDesignBlock => internal.usesClkRst.usesRst case _ => false } || reversedDependents.getOrElse(domainOwner, Set()).exists(_.usesClkRst.usesRst) || - domainOwner.isTop && (domainOwner.getExplicitCfg.rstCfg match + domainOwner.isTop && + (domainOwner.getExplicitCfg.rstCfg match case RstCfg.Explicit(inclusionPolicy = ClkRstInclusionPolicy.AlwaysAtTop) => true case _ => false) end extension @@ -1099,7 +1102,8 @@ final case class DB( domainOwner.getDomainClkConstraintsView.foreach { case constraints.IO(loc = loc: String) => locationMap.get(loc).foreach { prevPort => - locationCollisions += s"${prevPort} and ${domainOwner.getFullName} are both assigned to location `${loc}`" + locationCollisions += + s"${prevPort} and ${domainOwner.getFullName} are both assigned to location `${loc}`" } locationMap += loc -> domainOwner.getFullName foundLoc = true @@ -1121,14 +1125,17 @@ final case class DB( case constraints.IO(bitIdx = None, loc = loc: String) => bitSet.clear() locationMap.get(loc).foreach { prevPort => - locationCollisions += s"${prevPort} and ${port.getFullName} are both assigned to location `${loc}`" + locationCollisions += + s"${prevPort} and ${port.getFullName} are both assigned to location `${loc}`" } locationMap += loc -> port.getFullName if (port.width != 1) - locationCollisions += s"${port.getFullName} has mutliple bits assigned to location `${loc}`" + locationCollisions += + s"${port.getFullName} has mutliple bits assigned to location `${loc}`" case constraints.IO(bitIdx = bitIdx: Int, loc = loc: String) => locationMap.get(loc).foreach { prevPort => - locationCollisions += s"${prevPort} and ${port.getFullName}(${bitIdx}) are both assigned to location `${loc}`" + locationCollisions += + s"${prevPort} and ${port.getFullName}(${bitIdx}) are both assigned to location `${loc}`" } locationMap += loc -> s"${port.getFullName}(${bitIdx})" bitSet -= bitIdx @@ -1176,7 +1183,8 @@ final case class DB( case constraints.IO(dir = dir: Dir) => (dir, port.modifier.dir) match case (Dir.IN, Dir.OUT) | (Dir.OUT, Dir.IN) => - errors += s"${port.getFullName} direction (${port.modifier.dir}) has a resource direction ($dir) mismatch." + errors += + s"${port.getFullName} direction (${port.modifier.dir}) has a resource direction ($dir) mismatch." case _ => case _ => } diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFMember.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFMember.scala index 91a13fe08..2cd431d5a 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFMember.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFMember.scala @@ -568,7 +568,8 @@ object DFVal: else Some(calcFuncData(dfType, op, argTypes, argData)) protected def `prot_=~`(that: DFMember)(using MemberGetSet): Boolean = that match case that: Func => - this.dfType =~ that.dfType && this.op == that.op && (this.args + this.dfType =~ that.dfType && this.op == that.op && + (this.args .lazyZip(that.args) .forall((l, r) => l =~ r)) && this.meta =~ that.meta && this.tags =~ that.tags @@ -796,11 +797,13 @@ object DFVal: protected def setMeta(meta: Meta): this.type = copy(meta = meta).asInstanceOf[this.type] protected def setTags(tags: DFTags): this.type = copy(tags = tags).asInstanceOf[this.type] override lazy val getRefs: List[DFRef.TwoWayAny] = - dfType.getRefs ++ meta.getRefs ++ List(relValRef) ++ (idxHighRef match - case ref: DFRef.TypeRef => List(ref); - case _ => Nil) ++ (idxLowRef match - case ref: DFRef.TypeRef => List(ref); - case _ => Nil) + dfType.getRefs ++ meta.getRefs ++ List(relValRef) ++ + (idxHighRef match + case ref: DFRef.TypeRef => List(ref); + case _ => Nil) ++ + (idxLowRef match + case ref: DFRef.TypeRef => List(ref); + case _ => Nil) def updateDFType(dfType: DFType): this.type = this def copyWithoutGlobalCtx: this.type = copy().asInstanceOf[this.type] def copyWithNewRefs(using RefGen): this.type = copy( @@ -931,7 +934,8 @@ final case class DFRange( ) extends DFMember derives ReadWriter: protected def `prot_=~`(that: DFMember)(using MemberGetSet): Boolean = that match case that: DFRange => - this.startRef =~ that.startRef && this.endRef =~ that.endRef && this.stepRef =~ that.stepRef && + this.startRef =~ that.startRef && this.endRef =~ that.endRef && + this.stepRef =~ that.stepRef && this.op == that.op && this.meta =~ that.meta && this.tags =~ that.tags case _ => false @@ -1280,7 +1284,8 @@ object DFConditional: protected def `prot_=~`(that: Pattern)(using MemberGetSet): Boolean = that match case that: Struct => - this.name == that.name && this.fieldPatterns + this.name == that.name && + this.fieldPatterns .lazyZip(that.fieldPatterns) .forall(_ =~ _) case _ => false @@ -1319,7 +1324,8 @@ object DFConditional: protected def `prot_=~`(that: Pattern)(using MemberGetSet): Boolean = that match case that: BindSI => - this.op == that.op && this.parts == that.parts && this.refs + this.op == that.op && this.parts == that.parts && + this.refs .lazyZip(that.refs) .forall(_ =~ _) case _ => false @@ -1688,7 +1694,8 @@ object TextOut: case _ => Nil protected def `prot_=~`(that: Op)(using MemberGetSet): Boolean = (this, that) match case (thisAssert: Assert, thatAssert: Assert) => - thisAssert.assertionRef =~ thatAssert.assertionRef && thisAssert.severity == thatAssert.severity + thisAssert.assertionRef =~ thatAssert.assertionRef && + thisAssert.severity == thatAssert.severity case _ => this equals that def copyWithNewRefs(using RefGen): this.type = this match case Assert(assertionRef, severity) => diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala index 7660baf37..51b26210f 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala @@ -438,8 +438,9 @@ final case class DFStruct( def getNameForced: String = name def width(using MemberGetSet): Int = fieldMap.values.map(_.width).sum def createBubbleData(using MemberGetSet): Data = fieldMap.values.map(_.createBubbleData).toList - def isDataBubble(data: Data): Boolean = - (fieldMap.values lazyZip data).exists((ft, fd) => ft.isDataBubble(fd.asInstanceOf[ft.Data])) + def isDataBubble(data: Data): Boolean = (fieldMap.values lazyZip data).exists((ft, fd) => + ft.isDataBubble(fd.asInstanceOf[ft.Data]) + ) def dataToBitsData(data: Data)(using MemberGetSet): (BitVector, BitVector) = (fieldMap.values lazyZip data) .map((ft, fd) => ft.dataToBitsData(fd.asInstanceOf[ft.Data])) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala index 767bcbdf3..e74751047 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala @@ -205,16 +205,16 @@ protected trait DFDataPrinter extends AbstractDataPrinter: def csDFOpaqueData(dfType: DFOpaque, data: Any): String = s"${csConstData(dfType.actualType, data).applyBrackets()}.as(${dfType.name})" def csDFStructData(dfType: DFStruct, data: List[Any]): String = - dfType.name + dfType.fieldMap - .lazyZip(data) - .map { case ((n, t), d) => - s"$n = ${csConstData(t, d)}" - } - .mkStringBrackets - def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = - (dfTypes lazyZip data) - .map((t, d) => csConstData(t, d)) - .mkStringBrackets + dfType.name + + dfType.fieldMap + .lazyZip(data) + .map { case ((n, t), d) => + s"$n = ${csConstData(t, d)}" + } + .mkStringBrackets + def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = (dfTypes lazyZip data) + .map((t, d) => csConstData(t, d)) + .mkStringBrackets def csDFUnitData(dfType: DFUnit, data: Unit): String = "()" def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String = data match diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala index 0b71f096e..1093432d4 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala @@ -168,8 +168,7 @@ case object AddClkRst extends Stage: val updatedDFVal = dfVal match // existing clocks also get the constraints from the domain owner case clk: DFVal.Dcl if clk.isClkDcl => - val updatedAnnotations = - (ownerClkConstraints ++ clk.meta.annotations).distinct + val updatedAnnotations = (ownerClkConstraints ++ clk.meta.annotations).distinct clk.copy( dfType = opaqueReplaceMap(dfType), meta = clk.meta.copy(annotations = updatedAnnotations) diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala index e062a8dd9..e22d9ee69 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala @@ -167,15 +167,17 @@ case object DropStructsVecs extends Stage: case _ => elemIdxVal.asValAny.asInstanceOf[IntParam[Int]] val elemWidth = elemSel.asValAny.widthIntParam val relValWidth = relVal.asValAny.widthIntParam - idxLow = (relValWidth - elemWidth * (elemIdx + 1)) + idxLow - .asInstanceOf[IntParam[Int]] + idxLow = (relValWidth - elemWidth * (elemIdx + 1)) + + idxLow + .asInstanceOf[IntParam[Int]] case rangeSel: DFVal.Alias.ApplyRange => val elemWidth = replacementMap(relVal).dfType.asInstanceOf[DFVector] .cellType.asFE[DFTypeAny].widthIntParam val relValWidth = relVal.asValAny.widthIntParam - idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) + idxLow - .asInstanceOf[IntParam[Int]] + idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) + + idxLow + .asInstanceOf[IntParam[Int]] case fieldSel: DFVal.Alias.SelectField => var relBitLow: IntParam[Int] = idxLow val dfType = replacementMap(relVal).dfType.asInstanceOf[DFStruct] @@ -205,8 +207,9 @@ case object DropStructsVecs extends Stage: case _: DFStruct => false case _ => true val bitsMeta = if (requireCast) partial.meta.anonymize else partial.meta - val idxHigh: IntParam[Int] = - (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]] + val idxHigh: IntParam[ + Int + ] = (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]] val bitsVal = dfhdl.core.DFVal.Alias.ApplyRange( relVal.asValOf[Bits[Int]], diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala index 3341f7b90..15759b249 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/ToED.scala @@ -160,11 +160,12 @@ case object ToED extends Stage: }.toList // create a combinational process if needed val hasProcessAll = - !domainIsPureSequential && (dclChangeList.nonEmpty || processBlockAllMembers.exists { - case net: DFNet => true - case ch: DFConditional.Header => true - case _ => false - }) + !domainIsPureSequential && + (dclChangeList.nonEmpty || processBlockAllMembers.exists { + case net: DFNet => true + case ch: DFConditional.Header => true + case _ => false + }) if (hasProcessAll) process(all) { val inVHDL = co.backend.isVHDL @@ -256,7 +257,9 @@ case object ToED extends Stage: block ) val hasSeqProcess = - clkCfg != None && (dclREGList.nonEmpty || processBlockAllMembers.nonEmpty && domainIsPureSequential) + clkCfg != None && + (dclREGList.nonEmpty || + processBlockAllMembers.nonEmpty && domainIsPureSequential) if (hasSeqProcess) if (rstCfg != None) diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala index bf1d3b878..85f101878 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala @@ -85,7 +85,8 @@ protected trait VerilogValPrinter extends AbstractValPrinter: val cellWidth = dfType.cellType.width val length = dfType.cellDimParamRefs.head.getInt val ret = for (i <- 0 until length) - yield s"${dfVal.getName}[$i] = ${initVal.getName}[${(length - i) * cellWidth - 1}:${(length - i) * cellWidth - cellWidth}];" + yield s"${dfVal.getName}[$i] = ${initVal.getName}[${(length - i) * cellWidth - + 1}:${(length - i) * cellWidth - cellWidth}];" ret.mkString("\n") case Func(op = Func.Op.++, args = args) => args.view.zipWithIndex diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala index c53f8cdb2..94cd679ee 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala @@ -80,12 +80,13 @@ protected trait VHDLDataPrinter extends AbstractDataPrinter: def csDFOpaqueData(dfType: DFOpaque, data: Any): String = csConstData(dfType.actualType, data) def csDFStructData(dfType: DFStruct, data: List[Any]): String = - printer.csDFStructTypeName(dfType) + dfType.fieldMap - .lazyZip(data) - .map { case ((n, t), d) => - s"$n = ${csConstData(t, d)}" - } - .mkStringBrackets + printer.csDFStructTypeName(dfType) + + dfType.fieldMap + .lazyZip(data) + .map { case ((n, t), d) => + s"$n = ${csConstData(t, d)}" + } + .mkStringBrackets def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = printer.unsupported def csDFUnitData(dfType: DFUnit, data: Unit): String = printer.unsupported def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String = diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala index 748258089..6bf95a11a 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala @@ -113,10 +113,11 @@ protected trait VHDLValPrinter extends AbstractValPrinter: case DFString => args.map(_.refCodeString).mkString(" & ") case dfType @ DFStruct(_, _) => - printer.csDFStructTypeName(dfType) + dfType.fieldMap - .lazyZip(args.map(_.refCodeString)) - .map { case ((n, _), d) => s"$n = $d" } - .mkStringBrackets + printer.csDFStructTypeName(dfType) + + dfType.fieldMap + .lazyZip(args.map(_.refCodeString)) + .map { case ((n, _), d) => s"$n = $d" } + .mkStringBrackets // all args are the same ==> repeat function case _ if args.view.map(_.get).allElementsAreEqual => diff --git a/compiler/stages/src/test/scala/StagesSpec/ExplicitCondExprAssignSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ExplicitCondExprAssignSpec.scala index f72bb7255..b41196935 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ExplicitCondExprAssignSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ExplicitCondExprAssignSpec.scala @@ -98,10 +98,11 @@ class ExplicitCondExprAssignSpec extends StageSpec(stageCreatesUnrefAnons = true val lhs = Bits(8) <> IN val shifted = lhs << 1 val o = Bits(8) <> OUT - o <> (( - if (lhs(7)) shifted ^ h"1b" - else shifted - ): Bits[8] <> VAL) + o <> + (( + if (lhs(7)) shifted ^ h"1b" + else shifted + ): Bits[8] <> VAL) end xtime val id = (new xtime).explicitCondExprAssign assertCodeString( diff --git a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala index 8898a807e..153407ddb 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala @@ -118,10 +118,11 @@ class ExplicitNamedVarsSpec extends StageSpec: val lhs = Bits(8) <> IN val shifted = lhs << 1 val o = Bits(8) <> OUT - o <> (( - if (lhs(7)) shifted ^ h"1b" - else shifted - ): Bits[8] <> VAL) + o <> + (( + if (lhs(7)) shifted ^ h"1b" + else shifted + ): Bits[8] <> VAL) end xtime val id = (new xtime).explicitNamedVars assertCodeString( diff --git a/core/src/main/scala/dfhdl/compiler/patching/Patch.scala b/core/src/main/scala/dfhdl/compiler/patching/Patch.scala index e8577a617..b3e58b6c1 100644 --- a/core/src/main/scala/dfhdl/compiler/patching/Patch.scala +++ b/core/src/main/scala/dfhdl/compiler/patching/Patch.scala @@ -349,16 +349,20 @@ extension (db: DB) tbl + (m -> Patch.Add(add.db, Patch.Add.Config.ReplaceWithFirst())) // add followed by a replacement is allowed via a tandem patch execution case (add: Patch.Add, replace: Patch.Replace) if add.config == Patch.Add.Config.After => - tbl + (m -> Patch.Add( - add.db.copy(add.db.members.head :: replace.updatedMember :: add.db.members.drop(1)), - Patch.Add.Config.ReplaceWithFirst() - )) + tbl + + (m -> Patch.Add( + add.db.copy(add.db.members.head :: replace.updatedMember :: + add.db.members.drop(1)), + Patch.Add.Config.ReplaceWithFirst() + )) // replacement followed by an add via a tandem patch execution case (replace: Patch.Replace, add: Patch.Add) if add.config == Patch.Add.Config.After => - tbl + (m -> Patch.Add( - add.db.copy(add.db.members.head :: replace.updatedMember :: add.db.members.drop(1)), - Patch.Add.Config.ReplaceWithFirst() - )) + tbl + + (m -> Patch.Add( + add.db.copy(add.db.members.head :: replace.updatedMember :: + add.db.members.drop(1)), + Patch.Add.Config.ReplaceWithFirst() + )) // allow the same member to be removed more than once by getting rid of the redundant removals case (Patch.Remove(isMovedL), Patch.Remove(isMovedR)) => tbl + (m -> Patch.Remove(isMovedL || isMovedR)) diff --git a/core/src/main/scala/dfhdl/core/DFDecimal.scala b/core/src/main/scala/dfhdl/core/DFDecimal.scala index 08d6961c7..ac785b48e 100644 --- a/core/src/main/scala/dfhdl/core/DFDecimal.scala +++ b/core/src/main/scala/dfhdl/core/DFDecimal.scala @@ -1055,7 +1055,8 @@ object DFXInt: end extension type ArithOp = - FuncOp.+.type | FuncOp.-.type | FuncOp.*.type | FuncOp./.type | FuncOp.%.type | FuncOp.max.type | FuncOp.min.type + FuncOp.+.type | FuncOp.-.type | FuncOp.*.type | FuncOp./.type | FuncOp.%.type | + FuncOp.max.type | FuncOp.min.type given evOpArithIntDFInt32[ Op <: ArithOp, L <: Int, diff --git a/core/src/main/scala/dfhdl/core/DFDouble.scala b/core/src/main/scala/dfhdl/core/DFDouble.scala index 512fb277d..761cbe0ec 100644 --- a/core/src/main/scala/dfhdl/core/DFDouble.scala +++ b/core/src/main/scala/dfhdl/core/DFDouble.scala @@ -47,7 +47,8 @@ object TDFDouble: object Ops: given evOpArithDFDouble[ - Op <: FuncOp.+.type | FuncOp.-.type | FuncOp.*.type | FuncOp./.type | FuncOp.max.type | FuncOp.min.type, + Op <: FuncOp.+.type | FuncOp.-.type | FuncOp.*.type | FuncOp./.type | FuncOp.max.type | + FuncOp.min.type, LPA, L <: DFValTP[DFDouble, LPA] | Double, LP, diff --git a/core/src/main/scala/dfhdl/core/DFEnum.scala b/core/src/main/scala/dfhdl/core/DFEnum.scala index 3e4830f7f..b738d9143 100644 --- a/core/src/main/scala/dfhdl/core/DFEnum.scala +++ b/core/src/main/scala/dfhdl/core/DFEnum.scala @@ -19,13 +19,11 @@ object DFEncoding: abstract class Default extends StartAt(0) abstract class Gray extends Auto: - final def calcWidth(entryCount: Int): Int = - (entryCount - 1).bitsWidth(false) + final def calcWidth(entryCount: Int): Int = (entryCount - 1).bitsWidth(false) final def encode(idx: Int): BigInt = BigInt(idx ^ (idx >>> 1)) abstract class StartAt[V <: Int & Singleton](value: V) extends Auto: - final def calcWidth(entryCount: Int): Int = - (entryCount - 1 + value).bitsWidth(false) + final def calcWidth(entryCount: Int): Int = (entryCount - 1 + value).bitsWidth(false) final def encode(idx: Int): BigInt = BigInt(idx + value) abstract class OneHot extends Auto: diff --git a/core/src/main/scala/dfhdl/core/MutableDB.scala b/core/src/main/scala/dfhdl/core/MutableDB.scala index 4bc6dc3c4..f75423575 100644 --- a/core/src/main/scala/dfhdl/core/MutableDB.scala +++ b/core/src/main/scala/dfhdl/core/MutableDB.scala @@ -373,8 +373,9 @@ final class MutableDB(): else resource.allSigConstraints } // merge the existing constraints with the new constraints - val updatedSigConstraints = - (existingSigConstraints ++ newSigConstraints).merge.consolidate(dcl.width) + val updatedSigConstraints = (existingSigConstraints ++ newSigConstraints).merge.consolidate( + dcl.width + ) // merge all other annotations val updatedAnnotations = updatedSigConstraints ++ otherAnnotations dcl -> dcl.copy(meta = dcl.meta.copy(annotations = updatedAnnotations)) diff --git a/core/src/test/scala/CoreSpec/DFMatchSpec.scala b/core/src/test/scala/CoreSpec/DFMatchSpec.scala index dd585bfd3..11eba556b 100644 --- a/core/src/test/scala/CoreSpec/DFMatchSpec.scala +++ b/core/src/test/scala/CoreSpec/DFMatchSpec.scala @@ -178,10 +178,10 @@ class DFMatchSpec extends DFSpec: test("Trivial tuple match skip") { import dfhdl.hw.flag.scalaRanges assertCodeString("") { - val (ret, _) = - (0 until 8).foldLeft[(Byte <> VAL, Byte <> VAL)]((all(0), all(0))) { case ((p, a), _) => + val (ret, _) = (0 until 8).foldLeft[(Byte <> VAL, Byte <> VAL)]((all(0), all(0))) { + case ((p, a), _) => (p, a) - } + } } } diff --git a/internals/src/main/scala/dfhdl/internals/helpers.scala b/internals/src/main/scala/dfhdl/internals/helpers.scala index a6a1e7e29..22b1bdd6f 100644 --- a/internals/src/main/scala/dfhdl/internals/helpers.scala +++ b/internals/src/main/scala/dfhdl/internals/helpers.scala @@ -333,10 +333,11 @@ extension (str: String) def forceWindowsToLinuxPath: String = str.replaceAll("""\\""", "/") def simplePattenToRegex: Regex = val updatedPattern = - "^" + str - .replace(".", "\\.") // Escape dots to match literal dots - .replace("*", ".*") // Replace * with .* - .replace("?", ".") // Replace ? with . + "^" + + str + .replace(".", "\\.") // Escape dots to match literal dots + .replace("*", ".*") // Replace * with .* + .replace("?", ".") // Replace ? with . + "$" updatedPattern.r end extension diff --git a/lib/src/main/scala/dfhdl/platforms/resources/ToggleIO.scala b/lib/src/main/scala/dfhdl/platforms/resources/ToggleIO.scala index ff9be3a8b..59e10c87c 100644 --- a/lib/src/main/scala/dfhdl/platforms/resources/ToggleIO.scala +++ b/lib/src/main/scala/dfhdl/platforms/resources/ToggleIO.scala @@ -16,7 +16,8 @@ object ToggleIO: ExpectedActiveState[T], "Missing implicit expected active state for toggle resource `" + t.Out + - "`.\nTo fix this, add:\n `given ExpectedActiveState[" + t.Out + "] = " + t.Out + ".EXPECTED_ACTIVE_STATE`" + "`.\nTo fix this, add:\n `given ExpectedActiveState[" + t.Out + "] = " + t.Out + + ".EXPECTED_ACTIVE_STATE`" ] ): CanConnect[R, V] with def connect(resource: R, dfVal: V)(using DFC): Unit = diff --git a/lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala b/lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala index e26ef9766..63eb66674 100644 --- a/lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala +++ b/lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala @@ -113,7 +113,8 @@ class VivadoProjectTclConfigPrinter(using case configConstraint: constraints.DeviceConfig => configConstraint }.getOrElse(throw new IllegalArgumentException("No `@deviceConfig` constraint found")) if (bo.flash) - s"""\nwrite_cfgmem -format mcs -interface ${config.interface} -size ${config.sizeLimitMb / 8} -loadbit "up 0x0 ./${topName}.bit" -file ./${topName}.mcs""" + s"""\nwrite_cfgmem -format mcs -interface ${config.interface} -size ${config.sizeLimitMb / + 8} -loadbit "up 0x0 ./${topName}.bit" -file ./${topName}.mcs""" else "" def configFileName: String = s"$topName.tcl" def contents: String = diff --git a/lib/src/test/scala/AES/defs.scala b/lib/src/test/scala/AES/defs.scala index 961e571a2..8578d5f15 100644 --- a/lib/src/test/scala/AES/defs.scala +++ b/lib/src/test/scala/AES/defs.scala @@ -36,8 +36,7 @@ extension (lhs: AESByte <> VAL) // corresponding powers in the polynomials for the two elements. The addition is performed with // the XOR operation. @targetName("addByte") - @inline def +(rhs: AESByte <> VAL): AESByte <> DFRET = - (lhs.actual ^ rhs.actual).as(AESByte) + @inline def +(rhs: AESByte <> VAL): AESByte <> DFRET = (lhs.actual ^ rhs.actual).as(AESByte) private def xtime: AESByte <> DFRET = lhs.mapActual: lhs => val shifted = lhs << 1 diff --git a/plugin/src/main/scala/plugin/CustomControlPhase.scala b/plugin/src/main/scala/plugin/CustomControlPhase.scala index 18602d8db..8fdb735a8 100644 --- a/plugin/src/main/scala/plugin/CustomControlPhase.scala +++ b/plugin/src/main/scala/plugin/CustomControlPhase.scala @@ -623,7 +623,7 @@ class CustomControlPhase(setting: Setting) extends CommonPhase: Some(elems) case TypeApply(sym @ Select(sel, _), _) if sym.symbol == defn.Any_isInstanceOf => unapply(sel) - case _ => + case _ => None end SI object Struct: @@ -779,7 +779,8 @@ class CustomControlPhase(setting: Setting) extends CommonPhase: } if (idxHigh != -1) report.error( - s"""Cannot compare a value of ${selectorWidth} bits width (LHS) to a value of ${selectorWidth - idxHigh - 1} bits width (RHS). + s"""Cannot compare a value of ${selectorWidth} bits width (LHS) to a value of ${selectorWidth - + idxHigh - 1} bits width (RHS). |An explicit conversion must be applied.""".stripMargin, patternTree.srcPos ) diff --git a/plugin/src/main/scala/plugin/LoopFSMPhase.scala b/plugin/src/main/scala/plugin/LoopFSMPhase.scala index aee6df2e6..f481ecfdb 100644 --- a/plugin/src/main/scala/plugin/LoopFSMPhase.scala +++ b/plugin/src/main/scala/plugin/LoopFSMPhase.scala @@ -271,7 +271,8 @@ class LoopFSMPhase(setting: Setting) extends CommonPhase: List(domainTypeTree) ) if anonfun.toString.startsWith("$anonfun") && process.toString == "process" && - forever.toString == "forever" && domainTypeTree.tpe.widenDealias.typeSymbol.name.toString == "RT" => + forever.toString == "forever" && + domainTypeTree.tpe.widenDealias.typeSymbol.name.toString == "RT" => processAnonDefSym = dd.symbol processScopeCtxSym = scopeCtx.symbol Some(ProcessForever(scopeCtx, dd.rhs)) diff --git a/plugin/src/main/scala/plugin/MetaContextGenPhase.scala b/plugin/src/main/scala/plugin/MetaContextGenPhase.scala index e61e65ef9..c4ef192f6 100755 --- a/plugin/src/main/scala/plugin/MetaContextGenPhase.scala +++ b/plugin/src/main/scala/plugin/MetaContextGenPhase.scala @@ -153,7 +153,8 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase: val origApply = applyStack.head applyStack = applyStack.drop(1) if ( - fixedApply.tpe.isParameterless && !fixedApply.fun.symbol.ignoreMetaContext && !fixedApply.fun.symbol.forwardMetaContext + fixedApply.tpe.isParameterless && !fixedApply.fun.symbol.ignoreMetaContext && + !fixedApply.fun.symbol.forwardMetaContext ) fixedApply match // found a context argument @@ -390,8 +391,10 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase: tree match case Apply(Select(lhs, fun), List(rhs)) if (fun == nme.EQ || fun == nme.NE) && - (lhs.tpe <:< defn.IntType || lhs.tpe <:< defn.BooleanType || lhs.tpe <:< defn - .TupleTypeRef) => + (lhs.tpe <:< defn.IntType || lhs.tpe <:< defn.BooleanType || + lhs.tpe <:< + defn + .TupleTypeRef) => val rhsSym = rhs.tpe.dealias.typeSymbol if (rhsSym == dfValSym) report.error( @@ -399,7 +402,8 @@ class MetaContextGenPhase(setting: Setting) extends CommonPhase: pos ) case Apply(Select(lhs, fun), List(Apply(Apply(Ident(hackName), _), _))) - if (fun == nme.ZOR || fun == nme.ZAND || fun == nme.XOR) && hackName.toString == "BooleanHack" => + if (fun == nme.ZOR || fun == nme.ZAND || fun == nme.XOR) && + hackName.toString == "BooleanHack" => report.error( s"Unsupported Scala Boolean primitive at the LHS of `$fun` with a DFHDL value.\nConsider switching positions of the arguments.", pos diff --git a/plugin/src/main/scala/plugin/MetaContextPlacerPhase.scala b/plugin/src/main/scala/plugin/MetaContextPlacerPhase.scala index 2739af90e..f057ebfd8 100644 --- a/plugin/src/main/scala/plugin/MetaContextPlacerPhase.scala +++ b/plugin/src/main/scala/plugin/MetaContextPlacerPhase.scala @@ -237,7 +237,8 @@ class MetaContextPlacerPhase(setting: Setting) extends CommonPhase: case Apply(Select(New(Ident(n)), _), _) if n == StdNames.tpnme.ANON_CLASS => tree case _ if ( - tree.fun.symbol.isClassConstructor && tpe.isParameterless && !ctx.owner.isClassConstructor && + tree.fun.symbol.isClassConstructor && tpe.isParameterless && + !ctx.owner.isClassConstructor && !ctx.owner.isClassConstructor && tpe.typeConstructor <:< hasDFCTpe ) => val cls = newNormalizedClassSymbol( From 3aed9ed0c094184d63b3af360d41b65149118ba9 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Sat, 17 Jan 2026 17:25:08 +0000 Subject: [PATCH 3/3] Add 'Reformat with scalafmt 3.10.4' to .git-blame-ignore-revs --- .git-blame-ignore-revs | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 000000000..941b43ab2 --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +# Scala Steward: Reformat with scalafmt 3.10.4 +791ad4a57a45e7561ca2ebb6cdcb6f217dd15a8a