_BLANK_CS209P-RISCV-Simulator/cache_system.cpp at main · Codebank-Pranav-Tej-Ch-Network/_BLANK_CS209P-RISCV-Simulator · GitHub

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#include "cache_system.h"

CacheSystem::CacheSystem(int l1_lat, int l2_lat, int mem_lat)
    : l1i(1024, 64, 4, ReplacementPolicy::LRU), // 1KB, 64B block, 4-way
      l1d(1024, 64, 4, ReplacementPolicy::LRU), // 1KB, 64B block, 4-way
      l2(4096, 64, 8, ReplacementPolicy::LRU),  // 4KB, 64B block, 8-way Unified
      l1_latency(l1_lat),
      l2_latency(l2_lat),
      mem_latency(mem_lat) {}

AccessResult CacheSystem::accessInstruction(uint32_t address) {
    AccessResult result;
    result.l1_hit = false;
    result.l2_hit = false;
    result.total_latency = 0;

    // 1. Check L1I
    result.total_latency += l1_latency;
    l1i.access(address, result.l1_hit);

    if (result.l1_hit) {
        result.level_reached = "L1I";
        return result;
    }

    // 2. L1I Miss -> Check L2
    result.total_latency += l2_latency;
    l2.access(address, result.l2_hit);

    if (result.l2_hit) {
        result.level_reached = "L2";
        l1i.insertBlock(address); // Bring block to L1I
        return result;
    }

    // 3. L2 Miss -> Main Memory
    result.total_latency += mem_latency;
    result.level_reached = "Main Memory";

    // Fill hierarchy: Main Memory -> L2 -> L1I
    l2.insertBlock(address);
    l1i.insertBlock(address);

    return result;
}

AccessResult CacheSystem::accessData(uint32_t address, bool is_write) {
    AccessResult result;
    result.l1_hit = false;
    result.l2_hit = false;
    result.total_latency = 0;

    // 1. Check L1D
    result.total_latency += l1_latency;
    l1d.access(address, result.l1_hit);

    if (result.l1_hit) {
        result.level_reached = "L1D";
        // Handle write-through/back logic would go here if specialized
        return result;
    }

    // 2. L1D Miss -> Check L2
    result.total_latency += l2_latency;
    l2.access(address, result.l2_hit);

    if (result.l2_hit) {
        result.level_reached = "L2";
        l1d.insertBlock(address); // Bring block to L1D
        return result;
    }

    // 3. L2 Miss -> Main Memory
    result.total_latency += mem_latency;
    result.level_reached = "Main Memory";

    // Fill hierarchy: Main Memory -> L2 -> L1D
    l2.insertBlock(address);
    l1d.insertBlock(address);

    return result;
}

void CacheSystem::printStats() {
    std::cout << "\n========== CACHE HIERARCHY STATS ==========" << std::endl;
    std::cout << "L1 Instruction Cache: " << l1i.hits << " Hits, " << l1i.misses << " Misses" << std::endl;
    std::cout << "L1 Data Cache:        " << l1d.hits << " Hits, " << l1d.misses << " Misses" << std::endl;
    std::cout << "L2 Unified Cache:     " << l2.hits  << " Hits, " << l2.misses  << " Misses" << std::endl;
    std::cout << "===========================================\n" << std::endl;
}