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OQ1 · Sensor timing jitter (slotted-disk rig) #1

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@perfilev-dev

Open question #1 in docs/architecture.md §11 — the highest-risk item in the project. Per decision D15, no batch purchases, PCB orders, or public timelines until this passes.

Problem. A datasheet "≤ 1 ms response time" specifies delay, not repeatability. Timing accuracy lives in the jitter of the full path: beam → sensor → optocoupler → capture.

Test plan

  • Slotted disk on a motor at stable RPM breaking the beam; hundreds of cycles.
  • Measure timestamp spread with a logic analyzer (BOM 2.4).
  • Run the same rig on the brand-name sensor and on low-cost industrial clones (BOM basket 1, validation-first option).

Pass criteria. < 1 ms total path jitter (beam → timestamp).

The outcome decides

  • the sensor BOM — brand vs clone is a several-fold cost difference for the open BOM;
  • whether D12 (no line-scan photo finish) stands — see its "would change it" clause.

Independent reproduction is a top-tier contribution — report via the Bench validation result issue form or right here with raw data attached.

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    hardwareEnclosures, sensors, power, cabling, PCBhelp wantedExtra attention is neededvalidationBench validation of open questions (architecture.md §11)

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