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Replace design variable f with w to avoid Ansys intrinsic variable co… #55

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Replace design variable f with w to avoid Ansys intrinsic variable co…

Replace design variable f with w to avoid Ansys intrinsic variable co… #55

Workflow file for this run

.github/workflows/rull.yml at b19a136
name: Ruff
on:
push:
branches:
- main
pull_request:
jobs:
ruff:
runs-on: ubuntu-latest
steps:
- name: Checkout
uses: actions/checkout@v4
- name: Install Ruff
run: pip install ruff
- name: Ruff lint
run: ruff check .
- name: Ruff format check
run: ruff format . --check