Question: How is a complete TPU generated in RAG database?

[heimi2022]

Hello, I have a question regarding your project and hope you could clarify it:

I noticed that the fine-tuned model can only generate structured Verilog headers. However, in the RAG database, I could not find the top-level TPU file—only the submodules within the TPU. Could you please explain how a complete TPU design is generated?

I tried providing the structured Verilog headers from the training set to the RAG database, but I did not get the expected complete TPU result. Am I missing some steps, or could you explain the process by which the RAG database generates the full design?

Thank you very much for your help!